1. Field of the Invention
The present invention relates to a method of fabricating an integrated circuit. More particularly, the present invention relates to a method of fabricating a complementary metal oxide semiconductor (CMOS) device.
2. Description of Related Art
Along with the progress in the development of electronic devices such as communication electronic devices, the operating speed of transistors is growing faster. However, limited by the moving speed of electrons and holes in a silicon channel, the application range of transistors is also restricted.
A method using a mechanical stress in channel to improve the moving speed of electrons and holes in the channel is an effective way to eliminate the limitation caused by the scaling down of a device.
A conventional technique using a material such as SiGe expitaxy as a main component of a source/drain region of a transistor has been proposed. First, a portion of the substrate in which a source/drain region is predetermined to be formed is removed, and SiGe is refilled by using a selective area epitaxy growth technique. SiGe is used as the main component of the source/drain region. Compared with the material characteristics of Si, Ge has smaller electron effective mass and hole effective mass, so that the source/drain region formed by SiGe can increase the mobility of electrons and holes, thereby enhancing the performance of the device.
According to another method, after an ion implantation process in the source/drain region of the transistor and before a rapid thermal annealing (RTA) process, a layer of stress-transfer-scheme (STS) is covered on the substrate for providing a stress to a gate conductive layer, and then the STS is removed, such that the stress memory effect generated by the STS to the gate conductive layer is used to enhance the ion performance of the device.
However, if SiGe is used as the main component of the source/drain region and meanwhile the STS technology is adopted, the ion performance of the device cannot be effectively enhanced.
The reason is that the STS when applied in a conventional transistor device is deposited after the ion implantation process for forming a source/drain contact region is performed. The energy for the ion implantation process in the source/drain contact region is high enough to amorphize the polysilicon of the gate conductive layer into amorphous silicon, and the amorphous silicon has an excellent stress memory effect generated by the STS, so after the STS is removed, the stress memory of the amorphous silicon can improve the ion performance of the device.
However, when SiGe is used as the main component of the source/drain region, the SiGe expitaxy process is performed at a temperature up to 700° C.-900° C. for 3-4 hours, thus generating an over-high thermal budget, such that the gate conductive layer is recrystallized into polysilicon. The ion implantation process in the source/drain contact region of an n-type channel MOS (NMOS) is performed before the SiGe expitaxy process, so before the STS is formed, only an ion implantation process of low energy in a source/drain extension region is performed. However, the energy for the ion implantation process in the source/drain extension region is insufficient to completely amorphize the gate conductive layer into amorphous silicon, so the stress memory generated by the STS to the gate conductive layer is not sufficient to effectively enhance the ion performance of the device.